Course on secure hardware design of silicon chips

Course on secure hardware design of silicon chips

This paper describes the design and evaluation of a secure chip design module for graduate students and junior engineers with an electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. There a...

Asynchronous Design Methods for Dark Silicon Chips

The scaling of CMOS technologies continues to enable each two years more and more transistors to the ASIC designers and eventually application users. In theory this would mean that the processing architectures could also exponentially develop in the direction of further many-processor systems scaling. Nevertheless there are significant issues which may disable such scenario with the current (20...

Software/Hardware Co-Design of Efficient and Secure Cryptographic Hardware

Most cryptographic systems are based on the modular exponentiation to perform the non-linear scrambling operation of data. It is performed using successive modular multiplications, which are time consuming for large operands. Accelerating cryptography needs optimising the time consumed by a single modular multiplication and/or reducing the total number of modular multiplications performed. Usin...

Nanoslits in silicon chips.

Potassium hydroxide (KOH) etching of a patterned [100] oriented silicon wafer produces V-shaped etch pits. We demonstrate that the remaining thickness of silicon at the tip of the etch pit can be reduced to approximately 5 microm using an appropriately sized etch mask and optical feedback. Starting from such an etched chip, we have developed two different routes for fabricating 100 nm scale sli...

Vision Chips or Seeing Silicon